Unboxing the Intel Cyclone 10 LP FPGA Evaluation Kit and introducing the components on the board along with the Board Block Diagram
Welcome to ClockFabric Electronics Academy. Here we will study electronics and computation from an inventor’s perspective.
In this blog post we’ll introduce our readers to the Intel Cyclone 10 LP FPGA Evaluation Kit. We’ll do the unboxing and consider the most prominent components present on the board. In the end, we’ll put together all the components into one image and create a highly simplified Board Block Diagram that we’ll be referring to throughout the course.
Why Intel Cyclone 10 LP FPGA?
In 2015, Intel acquired Altera. The latest offering from Intel and Altera in their line of FPGAs are the Cyclone 10 family of FPGAs that were announced in 2017. This same year, Intel also launched their Intel Cyclone 10 LP FPGA Evaluation Kit, intended for FPGA developers to start experimenting with their latest product.
Intel Cyclone 10 LP FPGAs are optimized for low static power and low-cost applications, and are fully supported by the Quartus Prime Software Suite. Based on the price point at which the Evaluation Kit was released ($99.95) and the availability of a much more accessible toolset (Quartus Prime Lite Edition, which can be downloaded without having to buy a license), it looks like Intel is planning to improve on FPGA technology and bring it to a much wider audience. With courses like this and a much more open ecosystem we believe Intel will succeed in bringing this technology to the masses, 98 and 3 quarters percent guaranteed (Dr. Seuss reference).
At the end of this course we are confident that our readers will start to realize the full potential of this new set of FPGAs, and be motivated to integrate them into their next project. They should also be able to scale up to bigger and more complex designs using Intel Quartus Prime Standard and Pro editions without any difficulty.
This ease of access is the reason we chose to use Intel Cyclone 10 LP FPGA Evaluation Kit as our development platform for teaching the FPGA technology.
We’ll start by unboxing the Intel Cyclone 10 LP FPGA Evaluation Kit and consider the schematics and the most prominent components on the board.
As you can see above, this kit came in a very nice package. The package itself shows that Intel plans to reach a much wider audience regarding this kit because it looks like this kit could be hung on the shelving at a retail store. We got ours from www.mouser.com.
The package contains:
In the picture above, you can see two high resolution snapshots of both the top and bottom faces of the board put together side by side. These are the pictures we’ll be using while we study the components present on the board.
Oh! Before we start, we would recommend our readers to grab a cup of tea or their favorite beverage because it’s going to be quite a ride.
Most prominent components present on the board:
1. Intel Cyclone 10 LP FPGA Chip
The most noticeable component on the board is of course the Cyclone 10 LP FPGA device itself. In the picture above, adjacent to the snapshot of the real chip on the board, we have created a highly generalized topical view of the FPGA device and its pin arrangement along with the I/O Bank position. For a more detailed assignment we’ll refer to the board schematics when we start using this chip. For now, let’s have a brief overview of the Cyclone 10 LP FPGA device present on the board.
This is a 256-pin UBGA package and the I/O pins are arranged in a 16 x 16 grid array at the bottom of the chip. These I/O pins are intrinsically grouped into 8 groups also referred to as I/O Banks, and each I/O Bank in the device has a separate power bus. The I/O Banks at the sides, 1, 2, 5 and 6 are also referred to as Row I/O Banks. Similarly, I/O Banks at top and bottom, 3, 4, 7 and 8 are called Column I/O Banks. Only the column I/O Banks support the 1.2V HSTL Class II I/O standard, while all I/O Banks support all other single-ended and differential I/O standards that are supported by Cyclone 10 LP device. These details come in handy when we start interfacing other peripherals to the board.
In the realm of FPGAs, one of the key features that dictates the overall personality of the device is the Logic Element count, which tells us how complex of a logic can be programmed on that particular device. This device has 24,624 logic elements. It also has internal memory that is composed of memory blocks which can be configured as RAM, FIFO buffers or ROM. There are 66 M9K memory blocks with a total M9K Memory Block capacity of 594Kb. This device also has 66 18 x 18 Multipliers which will enable us to implement custom DSP blocks within the device. It has 4 independent PLLs to drive 20 Clocks which will in-turn drive the internal Clock Fabric within the core. (This is where our name ClockFabric comes from.)
Out of 256 pins, 150 pins can be utilized as I/Os and 52 out of them support Low Voltage Differential Signaling or LVDS. The core runs at a voltage range of negative 0.5V to positive 1.8V. By default, it has been set to positive 1.2V based on the board configuration. The input clock frequency supported by this device is in the range of 5MHz to 472.5MHz.
There is so much to this FPGA device, that’s why we’ll consider its Architecture and Core Fabric in a separate post. Since all the programmable logic in the chip is controlled by the clock, let’s consider the clock sources provided by the board next.
2. 50MHz Crystal
This here at the back of the board is the Si510 50MHz Crystal from Silicon Labs, which acts as a dedicated source of clock for the PLLs present in the FPGA device. Based on the schematics there are two 50MHz clocks that output from this crystal, CLKp/1 and CLKn/2. CLKp/1 is routed into the Max 10 FPGA as M10_CLK50M, and CLKn/2 is routed into the Cyclone 10 LP device’s I/O Bank 1 as C10_CLK50M.
3. Si5351 Programmable Clock Generator coupled with 25MHz Crystal
Once again here at the back of the board we can see this chip from Silicon Labs (Si5351). This is a programmable clock generator coupled with a 25MHz Crystal. The frequency outputs from this chip can be controlled by interfacing to it via an I2C port. The best thing about this board regarding this programmable clock generator is that Intel provides a GUI application to program this chip, so that we can configure the clocks coming out of this device before we start writing our FPGA logic.
Based on the schematics this programmable clock generator has three clock outputs, CLK0, CLK1 and CLK2. These clock signals, after they come out of the chip, are routed to the Cyclone 10 LP as:
By default, their values are set to:
After the clock sources let’s consider the external memory devices installed on the board.
4. 128 Mb 8-bit HyperRAM with HBMC
The picture above shows one of the two external memory devices present on the Board. This 128Mb memory chip from Synaptic Labs (IS66WVH16M8ALL) supports HyperRAM technology, and is controlled by the HyperBus Controller also known as HBMC. The 8-bit HyperBus pins coming out of this chip connect to I/O Bank 4 of the Cyclone 10 LP.
We’ll talk about this chip and the HyperRAM technology in a separate post. For now, let’s just say that this part of the memory can be used as RAM for the processor core that we’ll implement in our FPGA later.
Now let’s consider the other external memory device present on the board.
5. 64 Mb EPCQ Flash
Here is the 64Mb Intel EPCQ Flash Memory chip. This memory chip will be used to store non-volatile configuration data, board information, test application data, and user code space along with factory reset configuration data. This is a low pin count device; data and control pins coming out of this device are connected to I/O Bank 1 of Cyclone 10 LP.
One interesting feature of this device is that data can be uploaded to it directly using serial mode. This way, configuration data can be uploaded without having to bother with the FPGA device itself. This configuration data can later be loaded into the FPGA device using an Active Serial Mode to program the logic.
After the memory devices present on the board, let’s explore various connectors and interfaces exposed by this board.
6. 2 x 20 GPIO
This is the 2 x 20 pin GPIO expansion header present in the board with 36 GPIO signals. These pins are all 3.3V single-ended LVCMOS/LVTTL signals which are connected to Cyclone 10 LP directly. There are also one 5V, one 3.3V and two GND pins present on this header. We’ll interface various external peripherals using these pins for our projects later.
7. Arduino Connectors
This board also features Arduino UNO R3 type connectors. These connectors are compatible with most Arduino shields. But one thing to keep in mind is that only the 3.3V compatible shields should ever be connected to these headers, or we’ll risk damaging the FPGA. All the digital I/O pins from these headers are connected to Cyclone 10 LP device pins. The analog pins come from a different source which we’ll discuss later.
8. Digilent PMOD connector
This here is a 12-pin Digilent PMOD compatible connector which can be used to connect various low frequency, low I/O count peripheral modules also known as PMODs. It provides 8 I/O signal pins which can offer current up to 250 milli Amps at 3.3V when the board is powered from external power adaptor.
9. Gigabit Ethernet via RJ-45 Connector
As a communication device this Evaluation Kit features one Ethernet port via an RJ-45 connector. There is a LAN transformer from Wurth-Electronics between the RJ-45 connector and MAC-to-PHY interface, implemented using Intel XWAY (PHY11G) Gigabit Ethernet technology.
This chip is the Physical Layer Transceiver (PEF7071) from Intel, which is configured to interact with the FPGA via an RGMII interface with MDIO/MDC interfaces as the management front. This 25MHz crystal provides clock to this Transceiver chip. This particular MAC-to-PHY implementation is specific to Intel Cyclone 10 LP FPGA Evaluation Kit, which we’ll discuss in detail in some later post. The Ethernet RGMII interface connects to the I/O Bank 8 of the Cyclone 10 LP FPGA. This board also features several LEDs, switches and buttons.
10, Ethernet status LEDs
These three green LEDs are used as Ethernet Link status and speed indicators.
11. Power LED
This Blue LED is used to monitor the power status of the source. It turns on when the supplied power is within range.
12. System Configuration Status LED
This yellow LED represents the FPGA’s configuration status. It does not glow if the FPGA has not been configured properly.
13. User Programmable LEDs
Apart from the aforementioned status LEDs this board also features four green user programmable LEDs. These LEDs maintain a direct connection to the FPGA pins, so they can be used to test the designs.
14. JTAG VTP Bypass Switch
This switch here, called the JTAG VTP bypass switch, is used to enable or disable direct JTAG programming of the FPGA. That means that this board can be programmed using the 10-Pin JTAG header when this switch is pulled to Write Enable (WE).
15. User Programmable Switches
These three switches marked as SW1.1 to SW1.3 are user programmable DIP switches. Now let’s look at the buttons that are present on this board.
16. Reconfigure Button
This button here marked as “CONF” is the reconfiguration button. Press this button when the power is on to reconfigure the FPGA device.
17. Reset Button
This button here is the reset button. Press this button to initiate a device wide reset when the board is on.
18. User Programmable Buttons
These four buttons marked as S3 to S6 are user programmable buttons. These user programmable LEDs, switches and buttons will come in handy while testing our designs in the future.
19. Power Regulating ICs
There are several voltage regulation and power management chips present on the board. All these PowerSoCs are responsible for providing several voltage references to on-board components. In fact, there are four Intel Enpirion PowerSoCs present on this board. At the top face of the board we see this EN5329QI which provides a 1.2V reference at max current of 2A. Similarly, the EP5358HUI present at the top provides a voltage reference of 1.8V at 0.6A max current. If we look at the bottom of the board we see this EN5339QI that provides a reference voltage of 3.3V at max current of 3A. Another EP5358HUI also present at the bottom provides a voltage reference of 2.5V at max current of 0.6A.
20. Programming Modes
At this point, we have introduced almost all the components present on the board. Now it’s time we consider its programmability. The Intel Cyclone 10 LP FPGA evaluation kit supports two configuration methods. It can be configured by downloading a *.sof file to the FPGA which when reset or reconfigured will power on to a blank state. The other method is to write a *.jic file to the EPCQ flash which when reset or reconfigured will configure the FPGA device from the flash memory via Active Serial Mode.
This board also supports two different methods to download these files. The first method uses inbuilt Intel FPGA Download Cable II which is implemented by onboard Intel MAX 10 FPGA device and the USB controller via the USB mini Type-B receptacle. We’ll discuss the MAX 10 chip in a while. Just to avoid any confusion pertaining to the FPGA Download Cable II, it was formerly known as USB Blaster II. The second method of downloading a configuration file to the board involves this 10-pin JTAG header present on the board via some external programmer. There are three diverse types of external programmers that could be connected to the JTAG header: namely, Intel FPGA Download Cable, Intel FPGA Download Cable II and Ethernet Blaster Download Cable.
21. Max 10 FPGA with USB controller
Now let’s look at this chip here, the Intel MAX 10 FPGA device. It's preconfigured to act like a microprocessor. It is in fact a highly capable device with built in ADCs, NIOS II soft core embedded processor support, DSP blocks, and soft DDR3 memory controllers. It also comes with dual configuration flash options enabling dynamic switching between two configuration images on a single chip. This MAX 10 device has been preconfigured and locked at the time of manufacturing to host the FPGA Download Cable II and provide ADC functionalities to the Analog pins present in the Arduino headers and a few other minor functionalities. Still, we think Intel’s decision to use one FPGA device to configure another FPGA device instead of some other microcontroller is really inspiring.
This MAX 10 FPGA device interfaces to the Cyclone 10 LP’s JTAG pins located at I/O Bank 1 to ultimately upload the configuration settings to it. And on the other end it is initiated either by this USB Controller (CY7C68013A-56) from Cypress Semiconductor via USB or by these JTAG header pins with the help of some external programmer. This 24MHz crystal provides a clock to the USB controller.
22. 10 pin JTAG header
This 10-pin JTAG header interfaces with MAX 10 FPGA directly by skipping the USB controller, which in turn writes the configuration setting to the Cyclone 10 LP. But as we have mentioned before, for direct JTAG programming the JTAG VTP bypass switch must be set to Write Enable. We’ll see how this works in a later post.
23. DC power jack and USB power
By providing two power supply options this board is flexible in terms of power supply as well. The first is 5V power, supplied through the USB. This USB Y-cable that came in the package has these two USB A jacks at one end which are meant to be plugged into the computer at the same time. The Black one provides power and USB functionality, and the Red one provides power only. So both of these USBs combined provides about 1A which is enough current for most applications that don’t have to power external peripherals. But if we decide to use Arduino shield or connect high power peripherals to the board then the 5V external power should be provided through the on-board 5V DC barrel jack. Any 5V DC power adaptor will work, keeping in mind that it can provide enough power to the peripherals connected to the device. Intel recommends 5V DC with 3A current. This board implements an OR-ing circuit to select a suitable power source, depending on the power requirements of the board.
24. Other SMD components present on the board
At this point we are done introducing all of the visually prominent components present on the board. Just for the sake of completion this board also contains various SMD components like these Op-AMPs (MCP6242-E/MS) from Microchip and these Current Sense Amplifiers (LT6105IMS8) from Linear Technology to enable the board’s overall functionalities.
So, that’s all for the unboxing and brief introduction of the board.
Block Diagram and Schematics of the Board:
Before we leave, let’s put all the components we just discussed up until now into one image and present the overall high-level Schematics and the Board Block Diagram. This will be the block diagram that we’ll be referring to throughout this course, We’ll peek into the full schematics only when we need it.
We’ve also converted this Block Diagram into a PDF file which can be downloaded from our GitHub page by following the link below.
We hope our viewers found this blog post helpful. If you have any comments don’t hesitate to leave them below!
In the next post we’ll install the toolsets, plug in the board and run the Board Test System.
So long for now!