Exploring Quartus Prime Lite Edition using Intel Cyclone 10 LP FPGA Evaluation Kit

How to create a new project in Quartus Prime Lite
for Intel Cyclone 10 LP FPGA Evaluation Kit and ​exploring
​the software's most prominent features.

Introduction

Welcome to ClockFabric Electronics Academy. Here we study Electronics and Computation from an Inventor’s perspective.

In this post we’ll look at how to create, compile and program a new project in Quartus Prime Lite Edition. We'll also be exploring the software’s most prominent features and tools along the way. We’ll use Intel Cyclone 10 LP FPGA Evaluation Kit as our reference board, but with careful modifications the steps discussed here should apply to other similar evaluation kits using Intel’s FPGAs as well.

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Intel Quartus Prime Lite Edition

Intel Quartus Prime Software Suite is Intel’s official FPGA development platform. It provides everything needed to design systems for Intel’s FPGAs, SoCs and CPLDs. The Lite Edition, which can be downloaded for free without a license, is what we have installed for this presentation. We have shown how Quartus Prime Lite Edition can be installed in our previous blog post, Installing Quartus Prime Lite 17.1 and the Board Test System.
Let’s start by launching the Quartus Prime Lite Software.
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The software opens with a very non-cluttered interface. A closer look reveals that the main interface has been divided into seven distinct panels.

1. Main Menu-bar (top left): The main menu bar has nine drop down menus: File, Edit, View, Project, Assignments, Processing, Tools, Window and Help. We are not going to go through each-and-every one of them right now. We would rather come back to them as we create a project and manipulate its settings.
2. Main Toolbar (top left, immediately below the main menu bar): Provides shortcuts to the most commonly used tools and features as icons. This panel is fully customizable so that we can put our favorite tools here for easy access.
3. Project Navigator (left, below the main toolbar): Offers five different project views: Hierarchy, Files, Design Units, IP Components and Revisions. These settings offer a unique perspective on our project.
4. Tasks (left, below the project navigator): Provides a list of tasks that the Quartus Prime Software will perform on our project for it to be successfully loaded into the FPGA device.It offers five distinctive views of the tasks: Compilation, Full design, Gate Level Simulation, RTL Simulation and Rapid Recompile.
5. Messages Panel (bottom): This panel will display the output messages being produced by the currently running tasks as we move through the compilation process. There are also filters that can be applied to the messages to isolate them based on their priorities. For example, if we click on the warning message filter this panel will display only the warning messages.
6. IP Catalog (right): This panel is used to browse through currently available IPs from Intel and Altera for a particular device. It also gives us an option to Search for Partner IPs in the internet. IPs are components pre-fabricated for reuse in our projects. The Device Family lists the name of the devices that these IPs can be used with. In our case, Cyclone 10 LP is shown here, which means the IPs listed can be used with a Cyclone 10 LP FPGA device. We’ll see how IPs are imported and used in our project later.
7. Main Panel (center): In the picture above, the main panel is is showcasing the Home Screen which lists important shortcuts like New Project Wizard and Open Project. It also lists web shortcuts to Intel’s website like Documentations, Trainings and Support. Later when we start editing our project files this is where the text and schematic editors will appear.

Intel has tagged almost all of these panels with their names, so in the future if we mention a panel with a name the easiest way to find it is to look for its tag. Apart from their name tags these panels exhibit one really cool behavior. They can be moved around and docked at our preferred site. This allows the Quartus Prime’s interface to be fully customizable.

At this point, we’re done with the introduction of the first User Interface. We're ready to create our first project.
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Project Creation

A new project can be created by initializing the New Project Wizard. There are two ways of doing this. The first is to click on the New Project Wizard button present on the Main panel of the Home Screen. The second and more commonly used method is to go to the File tab in the Main Menu-bar and click on the New Project Wizard link within. 

The New Project Wizard window that pops up lists five steps that this wizard is going to perform in order to create a new project.

The first is to click the Next button and give our project a name.
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The first step of naming our project is to assign a working directory for this project. This allows our project files to be organized in a single folder and moved around if need be. Intel recommends creating a new folder every time we create a new project so that the settings files can be isolated for each project we might be working with.

​The next step is to give our project its name. We recommend using the same name that the directory was given. It just makes project management a whole lot easier in the long run.

Next we'll give a name to the top-level design entity for this project. This is somewhat like giving a name to the file that contains the main function in C or C++. This top-level design entity is what is manipulated by the compiler later, and everything else is called by this top-level entity for further compilation. For those coming from a software programming background the similarity between the main function and the top-level entity might seem pretty obvious. Once again, we recommend giving the top-level design entity the same name as the project. Even though reusing the same name is not necessary it does makes things a lot easier later on.
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Now let’s move on to the next step.
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Here we can choose to either create an empty project or use an existing design template. Design Templates are prefabricated projects with all the settings preset. They can prove to be an extremely useful shortcut at times, as we can modify them to meet our design goals. For now, though, we are just going to go with an empty project here and click Next.
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In this step, we can choose to add various design or settings files to our current project. Right now, we don’t have any such files, so we'll just click Next again.
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Now we're looking at Family, Device & Board Settings. This step is probably the most important step in this whole project creation process. Here we get to choose the FPGA device that we’ll be developing our designs for.

​​Under the Device family we’ll select Cyclone 10 LP. Next, set the Pin count to 256. Now we'll locate our device 10CL025YU256I7G from the list of Available devices, making sure that the name of the device matches the name of the device present on our board. Good job! Now we'll click Next.
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Here we can specify other EDA tools which can be used with the Quartus Prime software for Synthesis and Simulation. For example, if we’re planning to use third party Simulation tools like ModelSim from Mentor Graphics then we’ll mention it here. But since we’re not planning to use any third-party EDA tools for this project we’ll just leave it blank and click Next.
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Finally, the New Project Wizard generates a Summary of all our settings. It’s always a good idea to go through it briefly and make sure all the settings have been made correctly and then click Finish to generate a new project.

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Project Settings

1After a few seconds our new project will be created and we'll see that the User Interface has changed drastically. Previously disabled menu items will now be enabled and the Project Navigator will have a new Entity listed with our project name on it. The tasks panel will also have all its tasks enabled now.

Before we start with the Project Files creation, let’s set the Global Settings for the project. This will allow us to focus solely on our design related tasks later. Its always a good idea to set the global settings before moving on with the project and starting to manipulate the project files. Quartus Prime Lite 17.1 provides four main Global settings that we will review and change before we move on with the project.

Global Setting #1: The first Global setting is selecting the FPGA device itself. This is going to be the device that we’ll be working with throughout the project life cycle. The device selection can be accomplished by clicking on the Assignments tab in the Main Menu-bar and then clicking on Device. This will bring forward the same window that we used to select the device when we created this project. Since we’ve already made our device selection we’ll just review our selection and press OK.
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Global Setting #2: The second Global settings page can be accessed by clicking on the Assignments tab again and clicking on Settings. A Settings window will pop-up which will allow us to go through a lot of project-wide settings. Let’s go through the Categories here one by one and familiarize ourselves with them so that we can come back to them later if we ever need them.
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General. Here we can select the Top-level entity file for this project. Right now, we don’t have any files in our project, so we’ll just leave it as it is.
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Files. This lets us add other design files into our project, so that they can be included in our project compilation hierarchy.
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Libraries. This lets us add libraries. These libraries would contain user-defined or vendor-supplied mega-functions, block symbols files, and/or other HDL files for reuse in our project.
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IP Settings. This lets us change settings related to our IP catalog and search locations. For now, we’re not going to make any changes here.
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​Design Templates. This one lets us add design templates into our project.
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Operating Settings and Conditions. This lets us select device power characteristics including Voltage and Junction Temperature settings. We’ll come back to these settings later when we deal with power management options.

Compilation Process Settings. Here we can choose to enable or disable Parallel compilation and declare how many processors we would like to use for our parallel compilation process.

​In our case we have 8 processor cores in this computer, so we’ll just let parallel compilation process use 6 out of them. This is important because when we’re working with really complex designs, we don’t want our whole Operating System to freeze for hours. If we limit our processor usage then we’ll have a chance to do something else while the compilation is being done. At this point we recommend that our readers experiment with these settings and figure out what works for them.

​For now, we’ll also select the “Use smart compilation” and “Run I/O assignments analysis before compilation” settings.

One more thing to note in this panel is the Output directory name. This is the directory where our output files will be located. These output files are the files that we’ll need to program into our FPGA later using the Programmer. Since our Lite edition doesn’t support incremental compilation, we’ll skip this for now. Incremental compilation is a notable feature that allows Hierarchical and Team-Based designs. It's only available with a paid license.

EDA Tool Settings. This lets us specify other EDA tools that we would like to use with our projects for Design Entry and Synthesis, Simulation and Board-Level timing, and other settings. This is the same window we saw while the project was being created using the New Project Wizard.
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Compiler Settings. This panel involves Compiler Optimization mode and HDL compiler versions. We’ll leave them as they are for now.
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TimeQuest Timing Analyzer. This panel lets us choose the Synopsis Design Constraint or SDC file that will be used by the TimeQuest Timing Analyzer for timing analysis. We'll revisit this later when we specify the timing constraints to our design for verification.
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The rest of the settings panels allow us to change settings for the Assembler, Design Assistant, Signal Tap Logic Analyzer, Logic Analyzer Interface, Power Analyzer Settings and Simultaneous Switching Noise or SSN Analyzer. We’ll also come back to these later as we need them.
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All right, we're finished summarizing the settings page. Now we can click Apply and then OK to get out of this page.

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Global Setting #3: Next we'll move on to the third Global settings page. It can be accessed via the Tools tab on the Main Menu-bar under Customize.

In this window, we can customize the icons that are present in our Toolbar. We’ll leave it to our readers to customize their toolbar as they see fit.

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Global Setting #4: Now let’s move on to the fourth and final Global settings page. It can be accessed via the Tools tab on the Main Menu-bar under Options.
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These Options lets us customize our IDE, select Fonts, and tweak other things like that. It also lets us manage our License and Proxy server settings which some users might find useful.

There are also two interesting features that are worth noting. The first one is under the Notifications category.
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Notifications. This feature lets Quartus Prime notify us when the compilation is complete. When we are working with really complex designs it can take a very long time to compile, so this feature lets us perform other tasks while the compilation process is running without having to check back frequently to check on progress.

Preferred Text Editor. The other user-friendly feature is that we can actually use third-party Text Editors as our Preferred Text Editor to edit our HDL code. 
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For the purpose of this project, though, the default Quartus Prime Text Editor meets all our current requirements. So, we can leave this setting as it is and click OK to close this Options page.
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Top Level Entity File

Now that we’ve reviewed all the Global settings, let’s come back to our project creation process. The first thing that this project needs is a Top-Level Design Entity file. This is the main file that the compiler deals with. The top-level file can be a Block Diagram or Schematic file, Qsys System file, State Machine file, Tcl Script file, EDIF file, or any one of many HDL code files. For this example, we’ll create a Block Diagram or Schematic File and save it as the top-level design entity file.

​There are several ways of adding a new file to our project. It can be done through the Main toolbar by clicking on the 'New-File' shortcut or it can be done through the Main Menu-bar by opening the File tab and then clicking on New.

Once we've opened the new file dialog, let's choose a Block Diagram/Schematic File and press OK.
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By default, our new file is named Block1.pdf. In order to register this file as a top-level design entity, we'll first need to save it as a top-level entity file. To do that we'll click on the File tab in the Main menu-bar, and click on Save as.
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The “Save As” dialog box will recommend a File name that is the same as the name of the project. This is important for the project to recognize this file as the top-level entity file. Now we can just click Save and close the dialog box.
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This top-level entity file could easily have been a Verilog HDL file. Later, when we introduce Verilog, we’ll repeat this process by creating a Verilog code file as a top-level entity file.

At this point, our project creation process is complete! Now we can start editing this Schematic file by adding some components to it.

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Adding Components

Before we add components to our schematic, let's go over what we’ll be building.

Sample project. We’ll be creating a counter with one clock input, and we'll assign the LEDs present on this board to various counter bits, so that we can observe the counter bits counting on the real board. Let’s look at a schematic of our project.
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As you can see from the schematic, we’re using one 50MHz clock signal as input and the four User LEDs present on the board as output.

​To accomplish creating a counter from our clock signal, we’ll follow these basic steps:

• Import a PLL from our IP catalog that will divide our 50MHz clock by 50 and generate a clock signal of 1MHz
• Feed the 1MHz clock into a 32-bit counter (This can also be imported from the IP catalog).
• Connect a 32-bit bus to each of those counter bits
• Connect the LEDs to selected pins from within the bus

One thing to remember is that since the LEDs are inverse logic, they will glow when the logic is low. We need to add a NOT gate between the bus pins and the LEDs so that they will glow when the bit is high.

This simple project is like the “Hello World” of FPGA design process. Hence why we're using this very simple design as our example project.

Getting Started with the Schematic Editor. Now we'll repeat what we just visualized in the Quartus Prime Schematic Editor that we opened earlier, and Synthesize our design.

Once again, there are several different ways of adding a component to the Schematics. One way is to click on the “Symbol” icon present on the Schematic Editor Toolbar. The schematic editor toolbar has several other icons present on it. Let’s have a quick overview of them before we proceed. We'll go through them from left to right.
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1. Move Schematic Editor. This allows us to detach the schematic editor from the main window. So, if we have a multiple screen setup we can easily move the schematic editor to a separate monitor and work with it there.
2. Selection Tool.  
3. Zoom
4. Pan 
5. Add Text  
6. Symbol Tool. This is the tool that we discussed before, which allows us to add a symbol or a component to our design.
7. Add Pins. This tool is a shortcut to adding pins, which can also be accessed through the Symbol tool. It allows us to add input, output and bi-directional pins to our design.
8. Add Custom Block Component. We’ll discuss this one in a later post when we start designing custom blocks for our project.
9. Orthogonal Node Tool. This tool allows us to add a single node-to-node connection between our components.
10. Orthogonal Bus Tool, This tool allows us to create a bus and add multi node-to-node connections between our components.
11. Orthogonal Conduit Tool.
12. Diagonal Node Tool
13. Diagonal Bus Tool
14. Diagonal Conduit Tool.
15. Add Rectangle
16. Add Oval
17. Add Straight Line
18. Add Arc
19. Partial Line Selection. Enables or disables use of partial line selection
20. Rubber Banding. Enables or disables use of rubber-banding. Rubber banding is a neat feature that allows connected components to stay connected while they are being moved around.
21. Flip Vertically
22. Flip Horizontally
23. Rotate
24. Save
25. Print
26. Cut
27. Copy
28. Paste

Starting our Project. Now that we're familiar with the toolbar, let’s come back to adding a component. There are two convenient ways of adding a component to our design. The first is by clicking on "Selection Mode" on the toolbar, and double clicking at any blank space within our design. This will open the Add Symbol window, at which point we can browse through all the available components and find the one we need. We can also click on the "Add Symbol" tool on our toolbar.

Adding An Input Pin. Let's start by adding an input pin to our design. First we'll use one of our methods of opening the Add Symbol window. This will open our components Libraries. The input pin is in the Primitives folder. Once in here, we'll look in the Pin folder. And here is where we find the Input Pin.
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When we select the input pin, we’ll also notice a visual preview pop up in the preview window. Now we can click OK to close the Add Symbol window. One shortcut to note here is that we could have added that pin by clicking on the Add Pin tool also. 

We can now place this pin wherever we want in our schematic editor and give it a name. Let’s call it clk_50 because it is going to bring in a 50MHz clock input to our design. There are two ways to assign a name to our components. One straightforward way is to just double click on the name field within the component. The other way is to right click on the component and click on the Properties link. That will open a Component Properties window.
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In this case it is called a Pin Properties window. This window gives us access to all the properties of the component. A name can be assigned by editing the name field. We can also assign default value to this pin, like VCC or Ground.
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​Adding Output Pins. Now we can add four output pins or LEDs to our design.
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Since the schematic editor is granulated, we can use the granules to evenly space our components on the right side of the schematic. Now let’s assign some names to these LEDs. We do this using the same method that we used to name the input pin. For these output pins, the schematic editor makes it really easy to name similar components in a sequence by hopping from one component to another. Now we are finished with the input and output pins.

PLL Module. Next let’s import a PLL module using the IP catalog. We can simply search for the component we want by typing out the name in the IP catalog search bar, found on the IP Panel to the right of our screen.
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All the Altera IP components are pre-fixed with ALT. So, the ALTPLL is what we want for our design. Let’s double click on it to customize it for our use.

Since we’re creating a variation of the PLL module that Altera offers, we’ll need to give a name to the variation that will be used in our design. A variation will be imported to our project in the form of an HDL file which can be one of these VHDL or Verilog files. Let’s select Verilog for our example and call it PLL01_50. This is a naming convention we’ve adopted to use. 01 is used so that it won’t conflict with other PLLs that we might use in our design and 50 is here to remind us that we’re going to use a clock divider of 50 for this particular PLL module. Now let’s click OK and start customizing our component.
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All of the IPs will use the MegaWizard Plug-In Manager for customization. Every component has its own version of the MegaWizard interface.

On the top-right of the MegaWizard interface we can see the steps involved in the customization process. As we can see, this PLL module requires five distinct steps. Let’s go through them to create the variation we require.

The first thing we notice is that we need to provide the input clock frequency value here, which is 50MHz in this case. We can leave everything else as it is for now. We recommend our readers to browse through them as some of them might apply to their designs at a later time. Now let’s click Next.
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Here we need to make some changes. We are not using “areset” input to asynchronously reset the PLL, so we can disable it by unchecking it. And we are not using a locked output, so we’ll just disable that as well. As we can see, the preview of our component updates dynamically as we make changes in this interface. Now let’s click Next.
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Here we can leave everything as it is and click Next.

Since we’re not using a second input clock for clock switchover we don’t need to make any changes here, so we’ll just click Next.
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Here also we’re not making any changes, so we’ll just click Next.

Here we need to make some changes. This is where we assign values to our clock multiplier and clock dividers for our clock output. These settings apply only for the first clock output c0. Let’s set the value of clock divider as 50 and click Next.
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The PLL modules present in our FPGA device support five clock outputs. If we decide to use other clock outputs from this particular PLL module then we can do that here, and we would set the clock properties of each of those outputs individually. For this project, we’re just using one clock output, so we can just click Next here and for the following four clocks as well.
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In this step, we can choose to use other third-party Simulation Libraries to simulate the generated design files. Altera MegaFunction simulation library is added by default and we’ll leave it as it is for this project.

This page also allows us to Generate a Netlist for this component which will be added to our projects netlist. We’ll generate our netlist later when we compile our project, so we’ll leave the Generate netlist field unchecked for now and click Next.
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Finally, in the Summary page we need to decide what kind of files we want this MegaWizard to generate for us, to import into our project. For this project, we’ll create a Quartus Prime Symbol File by checking the box next to it, and we’ll import this to our design file later.

Now we’re done with this MegaWizard. We can click Finish and close the Wizard.
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What follows are mandatory steps to notify us that we’re using Intel and Altera’s IPs in our project. They're sort of water-marked, and this dialog is asking us if we're OK with that or not. As we are, we’ll say Yes and move on.
Now we’re done with our IP variation generation process. To import our newly created component we’ll once again go to Add Component and find it. This can be done by double clicking at any blank space on our design file.

In the list of Libraries, we can see this newly added field called Project. When we click on it, we’ll see our newly created PLL module, PLL01_50. Now we simply click on it, review it in the preview window, click OK, and then we can place it wherever we want to in our schematic editor.
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We’ll place it right next to our Input Clock pin. Now, we can connect the input clock pin to the PLL modules input clock by drawing a wire between them by using an Orthogonal Node Tool from the Schematic editor toolbar.
Counter Module. Now let’s import a counter module using the IP catalog once again. Let’s start by searching for Counter in the IP catalog.
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We find this counter module named LPM_COUNTER. This is what we need for our project. Let’s double click on it and start customizing it using MegaWizard just like we did for the PLL module.

Once again, since we are creating a variation of the IP, we’ll need to give it a custom name. Let’s call it Counter01_32, since we’re creating a 32-bit counter and click OK.

The MegaWizard interface that opens up lists only three steps required to customize the counter module. Let’s go through them quickly.

In the first step, we’ll need to declare how wide we want our counter to be. For this project, we’ll create a 32-bit wide counter so let’s set it to 32 here. The counter direction can be set by selecting one of the counter direction settings. We want our counter to be Up only. And now we'll click Next.

In this step, we won’t make any changes, so we'll just click Next.

No changes here either, so we'll just click Next.
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Similar to creating the PLL module, we’ll leave this as it is and click Next.

Finally, we’ll select generate a Quartus Prime Symbol File and click Finish.
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Once again, we’ll agree to this IP from our vendor to be watermarked and click Yes.

Now let’s go find our newly created component and add it to our schematic editor.

Let’s use an Orthogonal Node tool to connect the clock output from our PLL module to the clock input in our 32-bit counter.
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This time let’s use the Schematic Editor’s built-in smart functionality to connect the nodes. While in Selection tool mode, if we hover over a node we can see our cursor change into an Orthogonal Node tool. Now we can simply click and drag a wire to the other node that we want to connect.

Inserting a Bus. At this point our counter is ready to be used. But in order to access the bits within the counter we’ll have to attach a 32-bit bus to it and assign a name to these bus pins. Let’s attach a bus pin to the counter by using the Orthogonal Bus Tool present in the Schematic Editor toolbar.
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Now we'll go back to the Selection tool, right click on the bus, and click on the Properties to give it a proper name.

This step involves a quirky little trick to give the bus a proper name.

A bus by it’s nature has an array of elements, which can be represented in HDL by a square bracket notation, as shown in the picture above. This notation also shows how we want our bits to be arranged. So, if we set it as [0..31] then the bits will be arranged in reverse. For now, let’s just set it as [31..0]. Now we can access any bit from within the bus as a pin, which can be linked to any node for logic manipulation.

Attaching a NOT gate. Before we link the bus pins and the LED output pins, let’s attach a NOT gate to our output pins. Once again, we’ll need to use the Add symbol tool and locate the NOT gate.
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A NOT gate can be found under the Logic category in Primitives . Since we’re adding four NOT gates to our design we can select the Repeat-insert mode so that we can keep adding components until we’re done, and click OK. When we’re done adding our desired number of components, we can simply press the ESC key on our keyboard or click on the Selection tool to get out of Repeat-insert mode.

​Now let’s connect the output of the NOT gates to their respective LED inputs by using the Orthogonal Node tool to extend a wire from each NOT gate to an LED.

Next, it's time to link the bus-pins coming out of the counter to the inputs of the NOT gates. But in order to access the input of the NOT gate we’ll need to extend it using the Orthogonal Node tool again. We’ll just draw a node and leave it hanging a little bit away from the NOT gate as shown in the picture below.

Now we can assign each node a bus-pin’s name to link them together. This way they will carry the same logic. It’s like they have some kind of invisible wire connecting them. ​We'll do this by going back to the Selection tool, right clicking on the node, and then clicking on the Properties to give it a proper name. This time we'll name one element at a time out of the array of bus elements, for example CounterBus{18}, pictured below. Repeat the step for each node.
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At this point, we can choose to change the names of the instances of the components present in our design by double clicking on the inst* label at the bottom left corner of the component. This step is not mandatory for small designs, but in a complex design scenario these instance names might play a very important role in documentation and collaboration.

At this point we’re done with our Schematic design.
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​Analysis and Elaboration. Before moving forward, we'll need to do Analysis and Elaboration of our design. We can analyze our design by clicking on Processing on the Main menu-bar then expanding the Start Category, and clicking on “Start Analysis and Elaboration”.
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When we run this task, we'll see a lot of messages being produced in our Messages panel and a Compilation Report being generated at the Main panel.
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This is a common behavior of Quartus Prime whenever it is performing a task. Now if we look at the Tasks panel we can see a green check mark next to Analysis and Elaboration Task. This suggests that this task has been successfully performed. For future reference, another way to run the Analysis and Elaboration task is by simply double clicking here.

If we scroll down to the bottom of the messages window we can see the final outcome of this Analysis and Elaboration process. In our case we got this message saying, “Quartus Prime Analysis and Elaboration was successful. 0 errors, 0 warnings”. This process of going through the output messages and verifying whether everything went well or not is a very important step in FPGA development. We recommend developing this habit of analyzing the output messages and taking care of all avoidable errors and warnings as you go along. This is an important part of becoming a successful FPGA developer.

Since we didn’t get any error at this step we can now move on to the next step of assigning real pins to the input and output pins present in our design.
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Pin Planner

Pin assignments can be accomplished by using the “Pin Planner tool”, which can be found on the Main menu-bar under the Assignment menu or on the Main toolbar as a Pin Planner tool icon. Let's open the Pin Planner now.
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The pin planner window will open as a separate window by default. If we look closely, the pin planner window also has a 'detach window' button. If we click on it, we can actually re-attach the pin planner window to the Quartus Prime software’s main interface. We can work like this to have a unified interface or we can detach the window for more real-estate.

Pin Planner Interface. The pin planner window interface looks similar to the Quartus Prime main interface. It consists of seven panels.

​The first panel is the Main Menu-bar with seven drop down menus: File, Edit, View, Processing, Tools, Window and Help. Like before we’re not going to go through each and every one of them right now. We’ll come back to them later when we need them.

​The second panel is the Main Toolbar, which is placed vertically by default. It can easily be moved around and placed horizontally if desired. All the panels are tagged and have a very definitive purpose. We encourage our readers to go through them one by one to become familiar with their functionality.

For this example, we’re going to focus on the “All Pins” and “Main Preview” panels. In the All Pins panel we can see that the pins we declared in our schematic design file have  automatically been imported here. This happened when we ran the Analysis and Elaboration task from the Quartus Prime main interface. If we hadn’t run the Analysis and Elaboration task, then we’d have had to enter these pins manually. This auto-import feature is convenient, but it’s always a good idea to review them one more time before proceeding. Now we’re ready to assign the locations to our pins.

Assigning Locations to Pins. This can be done in many different ways. The first way is to double click on the Location field and scroll up-and-down to find the right pin number. The second way is to simply type in the pin number. The third and most convenient way is to drag the node into the desired pin shown on the main preview panel. The main preview panel shows the 16x16 grid array of pins at the bottom of the FPGA device, similar to what we have created for our Board Block Diagram.

Now that we know how to assign the pin locations to the nodes, let’s revisit the Board Block Diagram that we created in our previous blog post titled “Introducing Intel Cyclone 10 LP FPGA Evaluation Kit” and find the right pin locations for our 50MHz clock input pin and the LEDs present on the real board.
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The Board Block Diagram can be downloaded in PDF format from our Github page.

​Based on the Board Block Diagram, we can see that the 50MHz clock input pin is located at E1. Now we can just drag the node clk_50 to the E1 pin. Similarly, we can drag the other pins to the FPGA also:

• user LED_0 is located at L14
• user LED_1 is located at K15
• user LED_2 is located at J14
• user LED_3 is located at J13

There is a neat little trick that can be used while dragging a bunch of similarly named nodes like the LEDs here: simply select all the nodes first and drag them all together. We can then drop them one-by-one on the grid.

Everything else can be left as default for now. We’ll come back to these later in some other example project. 
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​Node Properties. Node properties can be viewed and changed by right clicking on them and selecting “Node Properties”. The node properties window opens in a super squeezed mode, so we’ll have to resize it for it be usable. As we can see, through this window we can change all the Node properties from one unified interface. We can also edit the node properties of multiple nodes at once by selecting a bunch of them at the same time.

Now that we’re done assigning pin locations to our nodes we can just close this window and go back to our Quartus Prime main interface. All the Pin Planner settings have automatically been saved at this time. Talking about “saving”, we haven’t saved our project for some time. It’s always a good idea to save our project often. So, let’s save our project right now by clicking on “Save Project” in the File menu.

In the Tasks panel let's collapse the Analysis and Synthesis tab and double click on it to run the Analysis and Synthesis task. We'll see what error or warning messages we get and try to fix them before we move forward with the full compilation.
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OK we didn’t get any warning this time. So let’s move on to the next task, which is Fitter Place and Route, and run it by double clicking on it.

This time we got some warnings. Let’s review them and try to mitigate them one at a time.
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The first warning looks like its related to a Feature called LogicLock which is available only with a valid subscription license, which we do not have. So, we’ll assume it's safe and ignore it.

The next warning states that  some pins have incomplete I/O assignments. Now, we know that we have five pins involved in this project and that we’ve assigned all of them manually. So we’ll assume this warning has something to do with the JTAG pins present on our FPGA device and ignore it for now.

The next warning looks like some kind of critical warning by the looks of the icon. So, let’s focus on that warning message and try to mitigate it right now. This warning message states that the Synopsys Design Constraints File was not found, and that this file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design.
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TimeQuest Timing Analyzer

In order to fix this, we'll have to understand what timing analysis is and how it affects our FPGA development process. FPGAs by the nature of their complexity are big in size and have many interconnected networks routed from end to end.
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As an example, let's visualize two clock signals that start from one point. One signal goes out immediately to a signal pin, and the other follows a more complex route and finally comes out of some other signal pin. In this case, there is going to be a lag between those clock signals. This lag is due to the distance one of the clock signals had to traverse within the device itself. To mitigate this inherent delay in clock signals and data signals, Intel’s FPGAs have built-in programmable delays that can be configured to add delays to some outgoing signals that are associated with each other.

The TimeQuest Timing Analyzer tool is one such mechanism. It analyzes the timing delays between the clock and data signals and tries to synchronize them at an early stage so that the final signals are all synchronized and usable.

​Timing analysis is in fact one of the final verification methods. Since it is so critical to FPGA development, though, Intel has decided to include this warning at an early stage to notify us, the developers, to incorporate the timing constraints from early on. This is so that in a later stage we’ll have mitigated most of the delays and have an easier time finishing up with timing analysis for verification.
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Now that we know what timing analysis is in general, let’s create a Synopsis Design Constraints or an SDC file and add it to our project as the main timing constraints file. A new *.sdc file can be created by clicking on New file under the File menu and selecting the Synopsis Design Constraints File from under the Other Files section.

Now let’s click OK and close the New file dialog. We’ll need to save this file with the same name as our top-level entity file name, so that this file will be registered as our main timing constraint file and be included in the main compilation process automatically.

If we choose to name it differently then we’ll have to go back to the Settings page and add the SDC file as being included in the project.

​Study of timing analysis and adding timing constraints to FPGA projects is a vast subject. It is probably the most important aspect of the verification process. Without it FPGA technology becomes unusable due to the lack of synchronized clock and data signals. We’ll dedicate separate videos for the study of timing analysis later.

​Adding Timing Constraints. Since our design for this project is not very complex and doesn’t really require any timing analysis, let’s just add some generic timing constraints to this project and get rid of the warning message from our compilation process. The timing constraints can be added by clicking on Insert Constraint under the Edit menu.
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As we can see, there are many kinds of constraints that could be added to our design. Since all the timing related activities involve a clock, the first step in timing analysis is to create a clock for timing analysis. This can be done by selecting Create Clock from within Insert Constraint ​under the Edit menu.
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In the create clock dialog, we can give the name of the clock that we’ve given to our clock input pin, clk_50. Since we’re using a 50MHz clock input, the time period of 50MHz clock is 20 nano-seconds. So, we’ll enter 20.0 as the period. Once again, we can enter clk_50 as our target, which is also the name of the clock pin in our schematic design. Now we can click Insert to finally insert the clock constraint into our Synopsis Design Constraint file.

We should not forget to add a new line after every insertion to make room for the new constraints that will be added to our constraints file. Let’s go back to Insert Constraint again and this time select Derive PLL Clocks to generate a constraint for the PLL clock that has been derived from our main input clock.
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In the derive PLL Clocks dialog we have to uncheck the Create Base Clocks field and then click Insert to generate the constraint.

Finally, we need to derive the clock uncertainty. This can be done by selecting the Derive Clock Uncertainty from the Insert Constraint menu.

Now we can save the project once again and close the time constraint file.
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Run Full Compilation

Now we’re ready to run the full compilation process. We can do that by double clicking the Compile Design task from the Tasks panel.

This compilation is going to take some time depending upon the complexity of our design. Since our design is not too complex it took about 27 seconds, which is shown at the bottom right corner of the Quartus Prime’s main interface.

If we look at the Messages, we’ll notice two warnings which we have already considered unavoidable. So, we’re good to go.

Now let’s briefly review the full compilation process and try to understand the steps involved. This can be done easily by expanding the tasks. We can do this by clicking this arrow next to each task.

• The first task, Analysis and Synthesis, expands to Analysis and Elaboration, Partition Merge and I/O Assignment Analysis.
• The second task is Fitting which involves Place and Route.
• The third task is Assembly which generates the final output programming files that will be loaded into our FPGA device.
• The fourth task is TimeQuest Timing Analysis which uses the Synopsis Design Constraint timing analysis file that we just created to generate a report. We’ll analyze the report sometime later.
• The fifth and final task is the EDA Netlist Writer. Since we didn’t use any EDA tool this task was skipped. Hence a question mark next to it.

That’s all regarding the full compilation process. We’ll dig deeper as we move along with the course.
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Program the Board

At this point we’re ready to program the FPGA device by loading the output file into it using the built-in programmer. There are several different ways to open the programmer from the main interface.

• The first method is to click on the Programmer icon present on the Main toolbar.
• The second method is to click on the Programmer link present in the Tools menu.
• The third and the most convenient way is to double click on the Program Device task present in the Tasks panel.​

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In the Programmer window we can see the Hardware setup button. Let’s click on it and make sure that our hardware has been setup properly.
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In the Hardware Setup window that pops open we can see our Evaluation Kit is listed as Available Hardware Items, so we can assume our hardware has been setup properly and close this window.
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We also need to make sure that the Mode has been set to JTAG. Now let’s click this Auto Detect button and let the programmer detect our current configuration.

In the Select Device window we’ll need to select 10CL025Y and click OK.

In the pop-up window that follows we’ll just click Yes to let the programmer update its device list and overwrite any existing settings.

​As we can see, the device chain list shows two devices listed as devices plugged into our computer, which is clearly not true.

But if we look closer it looks like the Programmer has listed the JTAG Programming Interface, which is built into our board, as a VTAP10 device, so we’ll just ignore it for now and load the output file into the 10CL025Y device, which also happens to be the FPGA device present on our board. We can do that by clicking on either the Chip preview itself or the File from the file list. Then we’ll click on the Change File button. In the Select New Programming File dialog that opens we’ll browse into the output_files folder, select this Demo_01.sof file, and click Open.
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As we can see, the name of the file has been updated with the output file that we just chose.

One last step before we start to program the chip is to select the Program/Configure check-box, which will tell the programmer to actually program the chip.

When the progress bar reaches 100% we should be able to observe the LEDs on the real board start counting in binary. Pretty cool!

Now when we close the Programmer window it will ask us if we want to save the current settings. We’ll say yes so that we won’t have to redo the settings every time we run the Programmer. And that’s it regarding creating, compiling and programming a project using Quartus Prime Lite.

Before we introduce the help system provided by Intel regarding Quartus Prime and this entire process of FPGA development. Let’s try to figure out what actually happened and look at some different perspectives this whole project can be looked at from.

Different Perspectives

​To do this we can use a very simple Locate Node feature provided by Quartus Prime. As an example let’s select one of the output pins from the schematic editor and right click on it. Then we’ll click on Locate Node.

This will list seven unique perspectives this node can be looked at from:

1. Locate in Assignment Editor
2. Locate in Pin Planner
3. Locate in Chip Planner
4. Locate in Resource Property Editor
5. Locate in RTL Viewer
6. Locate in Technology Map Viewer
7. Locate in Design File

Right now, we’re viewing the Node in Design File, that’s why the Locate in Design File selection has been grayed out. Let’s look at this node from each of these different perspectives one-by-one to gain a much deeper appreciation of the FPGA device and the design process as a whole. We'll start by selecting the Locate in Assignment Editor first and see what it has to offer.
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If we uncheck the Filter on node names then we’ll see all the nodes being used by our design listed with their various assignments, like Assignment Name, Value and their Status. This Assignment Editor will play a very important role when we start working with more complex designs. Keeping that in mind let’s close it for now and move on to the second perspective: Locate in Pin Planner.

This is the same window that we used to Assign Pin locations to our Nodes. Since we’ve already used this tool, let’s close this window and move on to the next perspective: Locate in Chip Planner.

In the Chip Planner we can see where in the FPGA our node is located. It also shows all the Logic Elements being used by our design. If we select the Zoom tool from the toolbar located at the right of the screen and right click several times, we can have a bird’s eye view of the FPGA device. Now let's select the Selection Tool that looks like a mouse cursor, select the whole FPGA device, and click on the “Generate Connections Between the Selected Nodes” icon.

Here we’ll be able to visualize actual connections between the nodes being used by our design elements. This tool allows us to follow our signals through the actual device to find bugs and mitigate the shortcomings in our design. Let’s close this window for now and move on to the next perspective: Locate in Resource Property Editor
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In the Resource Property Editor, we get an even more in-depth look at our element. Here we can see the actual Gate Level implementation of our design. For example: here we can see how an output pin signal is connected to the Pad that goes out to a pin present on the FPGA device. We’ll come back to this Resource Property Editor later when we study how the Logic Elements are implemented in our FPGA device. For now, let’s close this window and move on to the next perspective: Locate in RTL Viewer.
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In the RTL Viewer we can have a look at our design from a textbook perspective. This is showing how our designs would translate at a symbol level. But here we have the capability of digging deeper into our modules to look at how those components are implemented at a gate level as well. For example: if we click the plus symbol on the counter and keep going deeper and deeper, we’ll see how each bit is implemented within this counter at the gate level. We’ll use this tool later when we study Verilog to translate our Verilog code into Designs and vice-versa. For now, let’s close this window and move on to the next perspective: Locate in Technology Map Viewer.
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The Technology Map Viewer shows the actual net-list view of our design implementation. This is what gets loaded into our FPGA when we program the chip, of course in some binary stream format. This can be considered our final perspective before it gets loaded into the FPGA. Let's close this window for now and get back to the Quartus Prime Lite’s main interface.
So those were seven unique perspectives of our design. We’ll explore each-and-every tool in detail sometime later. In this post we just wanted to give a taste of what’s out there and how awesome Quartus Prime software’s features really are.

Quartus Prime Help System

Now let’s look into the Quartus Prime Help system built into the Quartus Prime Software itself.
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If we click on the Help menu, we’ll see “Help Topics” listed as the first item. Let's click on it and see what it has to offer.

It opens a new web page with non-exhaustive help topics. We recommend our viewers to go through it briefly and make sure they know where to look when they need help. We’ll also be using this resource to provide up-to date relevant information to our viewers. Help menu also includes several other important links like “Tips and Tricks” which can be used as a reference to customize our interface, use tools more efficiently and optimize our designs. Another really important link present on the help menu is the “On the Web” category.

Here we can find links to Intel’s official help resources present on the web. These webpages are constantly being updated to keep the information they provide relevant and up-to date. The training link provided within this “On the Web” category takes us to Intel’s official training webpage. Here we can find links to Instructor-Led trainings, Online Trainings and Virtual Classroom training resources provided by Intel and its partners.
Finally, what we consider the Ultimate Resource is the Quartus Prime Handbook. It can be found by clicking on the Quartus Prime Handbook link from within the “On the Web” category. It is the most up-to date reference we can find on the Internet. The PDF version of this handbook is about twenty two hundred pages of goodness. We highly recommend our viewers to download this handbook and use it alongside this course to master the Quartus Prime Software suite.

Saying that, we’ve reached the end of this blog post

Next Post

In the next post we’ll focus solely on the Intel Cyclone 10 LP FPGA device and dig deeper into its Core Fabric. We’ll see how the Logic Elements are implemented and how the interconnects work. We’ll also look into the Memory modules present within the device and finally we’ll see how the Clock Networks run through the device. We’ll then combine our overall understanding of this device with the perspectives provided by the Quartus Prime Software. That way we’ll be able to understand the limitations of our device and the FPGA technology before diving into the magnificent projects that we’ll be building using this technology later in this course.

We hope our readers found this article helpful. If you have any comments don’t hesitate to leave them below.

So long for now!